Problem 1. Using Verilog to design and test an arithmetic logic unit(ALU).ALU Module Design: This ALU has three inputs, two 32-bit signed inputs,one 3-bit ALUop input, and one 32-bit signed output.ALUOpFunction000and001or010add110subtract111sltALUOpTestbench Design: The test results should be printed on the screen withformat as below (for example):"1st Test data: input A is 1, input B is 2, ALUOp is 010, result is 3.""2nd Test data: input A is 3, input B is 4, ALUOp is 110, result is -1."
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