We are thrilled to announce that Cadence has successfully demonstrated first-pass silicon success of its UCIe™ standard package IP on Samsung Foundry's ...

IEEE Standard 1801, also known as Unified Power Format (UPF), is a standardized specification language designed to define the low-power architecture of an ASIC. It streamlines integration throughout ...

M31 Technology held an investor conference (March 19) and announced consolidated revenue of NT$1.48 billion for the full year ...

EnSilica is pleased to announce that it has been awarded a multimillion-pound design and manufacturing services contract by a ...

Brite Semiconductor today announced the launch of DDR3/4, LPDDR3/4 Combo IP. Developed on 28HKD 0.9V/2.5V platform, this IP has extensive protocol compatibility, supporting DDR3, DDR3L, DDR4 and ...

A new, comprehensive, end-to-end debug & trace solution for RISC-V based SoCs, Tessent UltraSight-V is specifically designed ...

FlexGen, a network-on-chip (NoC) interconnect IP, is aiming to accelerate SoC creation by leveraging AI.

Unprecedented growth and demand for edge computing and high-performance computing (HPC) is creating new opportunities and significant challenges for custom chips. We spoke to Sondrel CEO Oliver Jones ...

Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, has announced Platypus, the world’s first ...

To achieve this speedup, Synopsys announced at the GTC global AI conference that it is using NVIDIA CUDA-X libraries to optimize its solutions for next-generation semiconductor development. The ...

Omni Design Technologies, a leading provider of high-performance, low-power SWIFT™ data acquisition and signal-processing ...

TrendForce reveals that the combined revenue of the world’s top 10 IC design houses reached approximately US$249.8 billion in ...