GitHub

VHDL Module for the Digilent Asynchronous Parallel Port Interface (DEPP)

The DEPP.vhd module is designed as an Enhanced Parallel Port (EPP) interface for use with Digilent FPGA boards. It facilitates communication between a host computer and the FPGA via the Digilent Adept ...
GitHub

ATMI (Asynchronous Task and Memory Interface)

Asynchronous Task and Memory Interface, or ATMI, is a runtime framework for efficient task management in heterogeneous CPU-GPU systems. It provides a consistent API to create and launch tasks from ...
IEEE

Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation

Abstract: A clock and data recovery (CDR) module in 90nm CMOS, for a 10Gbps serial link, integrated with a -18dB attenuation channel, is presented. A novel dual-loop CDR with separate charge pumps for ...