Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh ...

Researchers from Yale University, Cornell University, Boston University, and NTT Research have published “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”.

Every new SoC tape-out demands broader coverage for design robustness, and the characterization workload has exploded. The ...

Exhaustive proofs are the only way to find deep corner-case bugs that can result in deadlocks and silent data corruption.

Thermal management has become the defining bottleneck in high-performance computing (HPC) and AI accelerator packaging. Modern packages integrate high-power ASICs with multiple High Bandwidth Memory ...

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?

As high-NA EUV approaches, mask makers need new metrics, model-based checks, and curvilinear-native data flows to keep turn ...

Over the past decade or so, foundation models have emerged as the dominant paradigm for interacting with language, images, ...

Cerebras’ IPO is a meaningful moment for the semiconductor industry — and not just for the financial implications. Their confidence in their opening price reflects something the industry has ...

Details Event Category: Events Location: Santa Clara Website: https://pr.tsmc.com/english/events/tsmc-events ...

Manufacturing, Packaging, Materials Navigating Increased Complexity In Advanced Packaging Intel Vs. Samsung Vs. TSMC Hybrid Bonding Makes Strides Toward Manufacturability 3.5D: The Great Compromise ...

Researchers from Micron Technology and Argonne National Laboratory have released “Understanding Inference Scaling for LLMs: ...