EDN

VHDL-AMS simulation for battery chargers

The Maxim 2003, and a parameterized NiCd battery model, were created using the VeriBest behavioural modelling language DIABLO. Although many SPICE simulators nowadays provide some high-level modelling ...
Design-Reuse

Xilinx Verilog module vs vhdl entity IP Listing

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ... The ...
Semiconductor Engineering

VHDL International

The objective of VHDL International was to extend and promote VHDL and to create other extensions to the language in cooperation with the IEEE. In addition, it had the objective to make the VHDL ...
Design-Reuse

Reusable VHDL IP in the Real World

Reuse has been an industry buzzword for years now. It is hardly a new idea, and probably goes back as far as the time when man first realised he could use the same fire both for keeping warm and for ...