In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry ...

High-level design (HLD) represents a hardware design at a more abstract level than register transfer level (RTL). A high-level synthesis (HLS) tool then can be used to produce the RTL necessary to ...

SystemC came into being due to the engineering demands to model System-on-Chips (SoCs). SoCs require that we model both hardware and software concurrently thereby increasing the level of complexity ...

Implementing advanced temporal assertions in SystemC is an error prone process due to the limited assertion capabilities of the class library. Current approaches ...

The challenge to produce higher density chips requires a change in the decade-old system design flow. We are at an inflection point similar to the move from schematic-based to hardware description ...

Synopsys is broadening its DesignWare silicon and verification IP portfolio by announcing the availability of a lineup of SystemC transaction-level models called the DesignWare System-Level Library.

A new technical paper titled “FMI Meets SystemC: A Framework for Cross-Tool Virtual Prototyping” was published by researchers at RWTH Aachen University, MachineWare and tracetronic. “As systems become ...

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...

With a new version 2.1 and its emphasis on transaction-level modeling, SystemC is finding its role as the glue that binds architectural analysis and the RTL implementation world. When the SystemC ...