Electronic Design

Cadence, Mentor Make Open Verification Methodology Available

The Open Verification Methodology (OVM) co-developed by Cadence Design Systems and Mentor Graphics is now available for free download from ovmworld.org. The Open Verification Methodology (OVM) ...
Electronic Design

Cadence, Mentor Enhance Open Verification Methodology

Cadence Design Systems and Mentor Graphics released an enhanced version of the source-code library and user documentation for the Open Verification Methodology (OVM), the industry's first open, ...
it.tmcnet

Cadence Design Systems Introduces Open-Source Reference Flow for SoC Verification

Electronic design company Cadence Design Systems Inc., announced plans to use open-source reference flow for verification of system-on-chip using Universal Verification Methodology standard. Engineers ...
EDN

Two giants unify SystemVerilog verification

London — Cadence Design Systems Inc. and Mentor Graphics Corp. have joined forces to promote a common approach to the verification of design files based on SystemVerilog. The Open Verification ...
CIOL

Cadence, Mentor make Open Verification available immediately

Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge. The OVM Web site is the central point of access for ...