EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
DIGITIMES

PGC Integrates 2.5D/3D Advanced Packaging Technology to Break the Memory Wall and Accelerate AI/HPC ASIC Innovation

As AI models and computing demands continue to grow exponentially, the biggest challenge in chip design is no longer pure processing power, but the bandwidth gap between processors and memory. Even ...
EDN

Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...
Design-Reuse

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
Hackaday

Opening Up ASIC Design

The odds are that if you’ve heard about application-specific integrated circuits (ASICs) at all, it’s in the context of cryptocurrency mining. For some currencies, the only way to efficiently mine ...
Semiconductor Engineering

In-Design Rail Analysis Is A Beautiful Thing

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ...
Electronic Design

Tool Tightens Timing In ASICs' Critical Paths

Deftly optimizing ASIC critical paths, this tool rides atop existing cell-based flows to improve timing while leaving physical design largely undisturbed. Deftly optimizing ASIC critical paths, this ...
Electronic Design

Mixed-signal ASIC Design Meets Tight Deadline

Emerson, AMIS complete mixed-signal project in less than 50 weeks, half the time generally needed to complete such a project Orders were up for Emerson Process Management’s largest-selling product ...
Semiconductor Engineering

Synopsys FPGA Platform: Enabling Faster Design, Verification and Debug of FPGAs

FPGA development teams are adopting ASIC-style design, verification and debug methodologies. Here are the necessary elements of such a flow. September 11th, 2019 - By: Synopsys Field programmable gate ...
Design-Reuse

Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications

SAN JOSE, Calif. -- March 12 2007--Altera Corporation (Nasdaq: ALTR) today announced that the U.S. Department of State has certified that the company's HardCopy(R) II structured ASIC design and ...